The Multicore Association Specifications


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  After Multicore Association (MCA) closed in 2020, Embedded Multicore Consortium (EMC) received several documents from MCA.  These files are open in this page with explanation in Wikipedia (referred on June 9, 2021).



●MCAPI V2.015  [PDF]  [Reference_card]   


  In 2008, the Multicore Communications API working group released the consortium's first specification, referred to as MCAPI. MCAPI is a message-passing API that captures the basic elements of communication and synchronization that are required for closely distributed (multiple cores on a chip and/or chips on a circuit board) embedded systems. The target systems for MCAPI span multiple dimensions of heterogeneity (e.g., core heterogeneity, interconnect fabric heterogeneity, memory heterogeneity, operating system heterogeneity, software toolchain heterogeneity, and programming language heterogeneity).


  In 2011, the MCAPI working group released MCAPI 2.0. The enhanced version adds new features, such as domains for routing purposes. MCAPI Version 2.0 adds a level of hierarchy into that network of nodes through the introduction of "domains". Domains can be used in a variety of implementation-specific ways, such as for representing all the cores on a given chip or for dividing a topology into public and secure areas. MCAPI 2.0 also adds three new types of initialization parameters (node attributes, implementation-specific configurations, implementation information such as the initial network topology or the MCAPI version being executed). The MCAPI WG is chaired by Sven Brehmer.



●MRAPI V1.0  [PDF]


   In 2011, the Multicore Resource Management API working group released its first specification, referred to as MRAPI. MRAPI is an industry-standard API that specifies essential application-level resource management capabilities. Multicore applications require this API to allow coordinated concurrent access to system resources in situations where: (1) there are not enough resources to dedicate to individual tasks or processors, and/or (2) the Run time (program lifecycle phase) system does not provide a uniformly accessible mechanism for coordinating resource sharing. This API is applicable to both SMP and AMP embedded multicore implementations (whereby AMP refers to heterogeneous both in terms of software and hardware). MRAPI (in conjunction with other Multicore Association APIs) can serve as a valuable tool for implementing applications, as well as for implementing such full-featured resource managers and other types of layered services. The MRAPI WG was chaired by Jim Holt.



●MTAPI V1.0  [PDF]  [Nutshell]  [Reference Card]


   In 2013, the Multicore Task Management API (MTAPI) working group released its first specification. MTAPI is a standard specification for an application program interface (API) that supports the coordination of tasks on embedded parallel systems with homogeneous and heterogeneous cores. Core features of MTAPI are runtime scheduling and mapping of tasks to processor cores. Due to its dynamic behavior, MTAPI is intended for optimizing throughput on multicore-systems, allowing the software developer to improve the task scheduling strategy for latency and fairness. This working group was chaired by Urs Gleim of Siemens.





  In 2013, the Multicore Programming Practices (MPP) working group delivered a multicore software programming guide for the industry that aids in improving consistency and understanding of multicore programming issues. The MPP guide provides best practices leveraging the C/C++ language to generate a guide of genuine value to engineers who are approaching multicore programming. This working group was chaired by Rob Oshana of NXP Semiconductors and David Stewart of CriticalBlue.



●SHIM 1.0  [PDF]


  In 2015, the Software-Hardware Interface for Multi-Many-Core (SHIM) working group delivered a specification to define an architecture description standard useful for software design. Some architectural features that SHIM describes are the hardware topology including processor cores, accelerators, caches, and inter-core communication channels, with selected details of each element, and instruction, memory, and communication performance information. This working group was chaired by Masaki Gondo of eSOL.


 Note that SHIM 2.0 was standardized as IEEE 2804-2019 (referred on June 9, 2021).